Question

A microprocessor has an increment memory direct instruction, which adds 1 to the value in memory location. The instruction has five stages: fetch opcode (four bus clock cycles); fetch operand address (four bus clock cycles); fetch operand (five bus clock cycles); add 1 to operand (three bus clock cycles) and, store operand (two bus clock cycles). By what amount (in percent) will the duration of the instruction increase if we have to insert four bus wait states in each memory read and memory write operation?

Answer 1

Given

Fetch opcode : 4 bus cycles - - - - - (a)

fetch operand address : 4 bus cycles - - - - (b)

fetch operand : 5 bus cycles - - - - -(c)

add 1 to operand : 3 bus cycles

store operand : 2 bus cycles   - - - - - -- (d)

Total number of cycles without inserting bus wait states is : 4+4+5+3+2 = 18 states.

Given we have to insert 4 wait states for each read and write operation so , we add 4 cycles to all the above instructions a, b ,c ,d

( don't need to add 4 cycles to operation "add 1 to operand " since it is not memory access operation)

So now total bus cycles is 8+8+9+3+6 = 34 states

Therefore percentage increase is (34 - 18)/18 x100 = 88.888%