Question

In a two-story voltage amplifier circuit, there is PNP on the first floor and NPN on the second floor. A total of 10 resistors and a total of 5 capacitors were used in the circuit, 5 resistors per floor. Re resistance of PNP transistor is 63.31 Ω and re resistance of NPN transistor is 15.25 Ω. The input impedance of the first floor is 212.36 Ω and the input impedance of the second floor is 9.1 K Ω. There is a voltage divider circuit at the entrance of both floors in the circuit. Thevenin equivalent voltage of the voltage divider circuit for the first floor is -1.5 V, and Thevenin equivalent voltage of the voltage divider circuit for the second floor is -5.43 V. The voltage gain of the first floor is Av1 = - 6.41. The two-layer voltage amplifier circuit can transfer a signal of up to Vi = 50 mV to the output without clipping. Design the circuit that provides the above specifications so that the supply voltage of the circuit is ± 15 V. (β = 200, VT = 26 mV, | VBE |=0.7.)

Answer #1

Design, simulate, and implement a multistage discrete amplifier
using small-signal BJT transistors.
Amplifier Specifications:
– Midband voltage gain: Av = 100.
– Lower 3-dB frequency: fc = 100 Hz.
– Input Impedance: Zin ≥ 250 kΩ.
– Output Impedance: Zo ≤ 100 Ω.
– Power Supply: Vcc = 15 V.
– The load resistance is 1 kΩ
– Output capability with a 1–kHz sinusoidal test signal must be
at least 2 V peak without severe distortion (i.e. clipping).
– Transistor...

-------Electronics 2-------
1. Design an amplifier using a MOSFET transistor
(2N7000) with a Common Source (CS) configuration with a resistor in
the Source. Its design should provide an amplification of -12V /
V.
2. The voltage Vcc will be +8 vDC, the AC voltage will
be 10 mV peak 5 kHz and the load resistance will be RL 2.2 kn.
3. Simulate the circuit in LTSpice. It must choose
resistors Ro, Rs, RG1 and RG2 such that the circuit operates...

Design the circuit of a source follower JFET amplifier biasing
circuit with load RL and input voltage internal resistance RS that
having a gain of +0.2. The specification of the circuit is given as
below: Supply voltage, VCC = +12 V; Input impedance, Zi = 10 k;
cut-off frequency from source capacitor, fLS = 40 Hz; cut-off
frequency from gate capacitor, fLG = 4 Hz; VGSQ = -2.86 V; IDSS =
16 mA and Vp = -4 V

Voltage amplifiers are available with Avoc = 8 V / V, Rin =
1.8 kΩ, Ro = 850 Ω. With a 12 V DC power source, each amplifier
consumes 1.5 mA average current.
a. How many amplifiers do you need to connect in cascade to
get at least a 1000 voltage gain with a load resistance of 1.0
kΩ?
b. What is the voltage gain Av obtained? (Respond with a
rounded whole number)
c. For the cascade connection, find the...

Using MultisimBlue – Advanced Circuit Simulation Design Program
make a
I. CE Swamped Amplifier Circuit producing the
following:
1. DC Current Gain: ?DC = 150 (minimum value) 2. AC Voltage
Gain: Av = 12 (minimum value)
II. Required Components:
1. Transistor Q1 – 2N2222A producing a VCE between 8 V to 12
V
2. Input AC Source: 10 mVAC (14.14 mVpk) @ 1 kHz
3. Coupling and Bypass Capacitors – 30 µF (suitable for low
frequencies)
4. Circuit VCC of...

circuit is composed of two parallel branches, the first contains
an impedance Z=3Ω + j4 Ω, and the second branch contains R=10Ω.
What is the power factor of the circuit:
Pf =
- Is it "lagging" or "leading"
What are the powers in the two resistors if the total power of
the circuit is 1100W:
P (in resistor 3Ω) = in W
P (in resistor 10Ω) = in W

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